3.1 Computer architecture

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Registers and the FDE Cycle

Watch this lesson Video 3.1.2 · 8:25 · What each register holds, which bus carries what, and why the program counter is incremented

1. CPU Registers

Registers are high-speed storage locations inside the CPU. Each one holds a single value the processor is working with at this instant.

Program Counter (PC)

Holds the address of the next instruction to be fetched.

Memory Address Register (MAR)

Holds the address of the current instruction or data being read from/written to memory.

Memory Data Register (MDR)

Holds the actual data or instruction fetched from memory (or waiting to be written).

Current Instruction Register (CIR)

Holds the instruction that is currently being decoded and executed.

Accumulator (ACC)

Holds the results of calculations performed by the ALU.

The pairing to remember: MAR and MDR always work together. The MAR holds where in memory, the MDR holds what was found there. One is an address, the other is contents.

2. System Buses

Buses are the physical connections (wires) that move data between the CPU and memory. They are not used for movement between two registers — registers are all inside the CPU already.

  • Address Bus: Carries addresses from the MAR to memory. (One-way / unidirectional).
  • Data Bus: Carries actual data/instructions between memory and the MDR. (Two-way / bidirectional).
  • Control Bus: Carries signals such as Read and Write from the Control Unit. (Two-way).

3. The Fetch-Decode-Execute (FDE) Cycle

This is the process the CPU repeats continuously, for as long as it is switched on, to run programs.

Step 1: Fetch
  • The PC contains the address of the next instruction.
  • That address is copied from the PC to the MAR. This happens inside the CPU — no system bus is involved.
  • The MAR places the address onto the Address Bus, which carries it out to memory, while the Control Unit sends a read signal along the Control Bus.
  • The contents of that memory location travel back along the Data Bus into the MDR.
  • The instruction is copied from the MDR to the CIR.
  • The PC is incremented by 1, so it now points at the following instruction.
Step 2: Decode

The Control Unit (CU) decodes the instruction held in the CIR, splitting it into its opcode (what to do) and operand (what to do it to), and works out which components need to act.

Step 3: Execute

The CPU carries out the instruction. If a calculation is required, the ALU performs it and the result is stored in the Accumulator (ACC).

Step 4: Repeat. Control returns to Fetch, and the whole cycle runs again using the address now in the PC. This is why the PC is incremented during fetch — so that the next pass picks up the next instruction rather than repeating the current one. A CPU performs this cycle billions of times per second, and its clock speed is simply how many times per second it can do so.

Worked example: two passes

Suppose memory holds an instruction LOAD 200 at address 100, and ADD 201 at address 101. Following the registers through:

StagePCMARMDRCIRACC
Start100————
PC → MAR100100———
Memory → MDR100100LOAD 200——
MDR → CIR100100LOAD 200LOAD 200—
PC incremented101100LOAD 200LOAD 200—
Decode + Execute10120025LOAD 20025
— cycle repeats —101101ADD 201ADD 20125

Notice two things in that trace. The PC changed from 100 to 101 during the first fetch, which is what makes the second pass collect a different instruction. And on the last row the MAR and MDR are reused — they are not dedicated to instructions, they are used again whenever memory is accessed for anything.

⚠️ Exam Warnings:
  • A common mistake is saying the "Data Bus carries addresses." Addresses go on the Address Bus; data goes on the Data Bus. Only the Address Bus is unidirectional (CPU → Memory).
  • PC to MAR does not use a bus. Both are registers inside the CPU. The buses only carry things between the CPU and memory.
  • Say that the cycle repeats, and link the PC increment to it. "The PC is incremented" earns more credit when you add "so the next instruction is fetched on the following cycle".