4.1 Central Processing Unit (CPU) Architecture

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CPU Architecture & The Von Neumann Model

1. The von Neumann Model

The von Neumann Model describes a computer design where:

  • There is a Central Processing Unit (CPU).
  • Program instructions and data are stored in a single Main Memory (RAM).
  • Instructions are fetched and executed sequentially.

2. CPU Components & Special Purpose Registers

Registers are high-speed storage locations inside the CPU itself.

PC (Program Counter)

Holds the address of the next instruction to be fetched.

MAR (Memory Address Register)

Holds the address of the memory location currently being accessed.

MDR (Memory Data Register)

Holds the actual data or instruction being moved to/from memory.

CIR (Current Instruction Register)

Holds the instruction that is currently being decoded and executed.

ACC (Accumulator)

Stores the results of mathematical and logical calculations from the ALU.

3. The System Bus

A "bus" is a set of parallel wires used to transmit data between components.

Bus Direction Function
Address Bus Unidirectional Carries the address of the memory location to be read from/written to.
Data Bus Bidirectional Carries the actual data/instructions between CPU and RAM.
Control Bus Bidirectional Carries signals from the Control Unit (e.g., Read/Write signals, Interrupts).

4. The Fetch-Execute (F-E) Cycle

1. FETCH: The address in the PC is copied to the MAR. The instruction is brought from RAM via the Data Bus into the MDR, then copied to the CIR. The PC increments by 1.
2. DECODE: The Control Unit (CU) looks at the instruction in the CIR to understand what needs to be done.
3. EXECUTE: The instruction is carried out. This might involve the ALU performing math or moving data between registers.

Fetch-Execute Cycle Visualizer

Trace the flow of data through registers using Register Transfer Notation (RTN).

100
0
0
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0
Current RTN: Idle
Click "Next Step" to begin the Fetch stage.
⚠️ AS-Level Focus: The Bus Width

The width of the data bus determines how many bits can be moved at once (e.g., a 64-bit bus is faster than a 32-bit one). The width of the address bus determines the maximum memory capacity the CPU can address.